1. Field of the Invention
The present invention relates to an imaging device.
Priority is claimed on Japanese Patent Application No. 2013-064876, filed Mar. 26, 2013, the content of which is incorporated herein by reference.
2. Description of Related Art
In imaging devices such as digital still cameras or video cameras, an auto focus (AF) function of automatically focusing on a subject is provided as a function related to imaging. In an AF function of a related art, so-called phase difference AF of controlling a position of a focus lens based on information of a phase difference between left light and right light received by an AF sensor mounted in an imaging device is performed. Further, in an imaging device having no AF sensor, high-frequency components are extracted from pixel signals output from respective pixels of a solid-state imaging device equipped in the imaging device, for example using a high pass filter (HPF). After that, a position of a focus lens is controlled based on values of the high-frequency components of the respective pixels. Such process is called “imager AF”.
In recent years, imaging pixels that output pixel signals obtained by performing photoelectric conversion on an optical image of a subject as imaging signals and either of the right and left sides are light-shielded in a region of pixels arranged in the solid-state imaging device, that is, an imaging region. Further, solid-state imaging devices in which focus detecting pixels that output pixel signals representing a quantity of received light of a left or right side of incident subject light as focus detection signals are arranged together have been proposed. An imaging device with such a solid-state imaging device calculates a phase difference using the focus detection signals output from the focus detecting pixels. Through this operation, the same AF function as in an imaging device that includes an AF sensor and performs phase difference AF, so-called filed phase difference AF, can be performed.
For example, Japanese Unexamined Patent Application, First Publication No. 2010-185998 discloses an example in which focus detecting pixels are arranged in an arbitrary row in a horizontal direction in an imaging region. Through the focus detecting pixels, focus detection of a subject image that changes in brightness in the horizontal direction can be performed. Further, Japanese Unexamined Patent Application, First Publication No. 2010-185998 also discloses an example in which focus detecting pixels are arranged in an arbitrary column in a vertical direction in the imaging region. Through the focus detecting pixels, focus detection of a subject image that changes in brightness in the vertical direction can be performed.
Further, Japanese Unexamined Patent Application, First Publication No. 2010-185998 also discloses a technique in which an imaging device reads focus detection signals from the focus detecting pixels arranged in the imaging region of the solid-state imaging device. In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-185998, the focus detection signals are read from the focus detecting pixels during a vertical blanking period of time rather than a period of time during which the solid-state imaging device outputs the imaging signals. In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-185998, the read focus detection signals are temporarily accumulated in a buffer equipped in a separating circuit that separates the imaging signals from the focus detection signals. The focus detection signals temporarily accumulated in the buffer are stored in a predetermined storage region of a dynamic random access memory (DRAM) equipped in the imaging device via a bus in the imaging device. When the focus detecting pixels are arranged at a plurality of positions in the imaging region, that is, when focus detection is performed at each of a plurality of positions, the focus detection signals of all positions are stored in the DRAM. Thereafter, in the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-185998, a phase difference calculation circuit that performs a correlation calculation between pixel columns and calculates a phase difference reads the focus detection signals stored in the DRAM. Further, a phase difference used to perform phase difference AF by the imaging device is calculated based on the read focus detection signals.
However, in the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-185998, the focus detection signals output from the focus detecting pixels are read using the vertical blanking period of time as described above. For this reason, when the solid-state imaging device operates at a high frame rate, it is difficult to secure a period of time necessary to read the focus detection signals. This is because as the frame rate of the solid-state imaging device increases, a period of time necessary to read the imaging signals is secured by reducing the vertical blanking period of time.
Further, in order to improve the focus detection accuracy in the imaging device, the density of the focus detecting pixels arranged in the imaging region of the solid-state imaging device should be increased. In other words, there are cases in which the number of focus detecting pixels arranged in the imaging region is increased. In this case, as the density of the focus detecting pixels arranged in the solid-state imaging device is increased, a long period of time is considered to be required for reading of the focus detection signals of the focus detecting pixels. Depending on the number of focus detecting pixels, it may be difficult to secure a period of time necessary to read the focus detection signals during the vertical blanking period of time.
A problem for securing a period of time necessary to read the focus detection signals can be solved by applying, for example, a technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2011-17842, to an imaging device. In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2011-17842, the focus detection signals are read together when the imaging signals are read from the solid-state imaging device. Techniques of separating the imaging signal from the focus detection signal through a separating circuit have been proposed. In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2011-17842, the focus detection signals are not read during the vertical blanking period of time. For this reason, even when it is difficult to secure a period of time necessary to read the focus detection signals during the vertical blanking period of time as the frame rate of the solid-state imaging device increases or as the density of the focus detecting pixels increases, the focus detection signals can be read, and the problem related to securing a period of time to read the focus detection signals can be solved.
Meanwhile, a technique for solving the problem of improving the focus detection accuracy in the imaging device is disclosed, for example, in Japanese Unexamined Patent Application, First Publication No. 2010-152161. In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-152161, the focus detecting pixels are arranged in a plurality of rows in the imaging region of the solid-state imaging device. The focus detection accuracy is improved by averaging the focus detection signals output from the respective focus detecting pixels and reducing an error related to arrangement positions of the focus detecting pixels in a subsequent calculation of a phase difference. In the solid-state imaging device disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-152161, a set of focus detecting pixels are not arranged in the same row or column in the imaging region, and a set of focus detecting pixels are separately arranged in two adjacent rows or columns as in the solid-state imaging device disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-185998.
FIGS. 10A, 10B, 10C, and 10D are timing charts illustrating an exemplary read timing at which focus detection signals are read from focus detecting pixels arranged in an imaging region of a solid-state imaging device according to a read technique of a related art. In FIGS. 10A, 10B, 10C, and 10D, at a timing synchronized with a horizontal synchronous signal HD, imaging signals and focus detection signals are read from respective pixels for each of rows of the imaging region of the solid-state imaging device, and only the focus detection signals separated by a separating circuit are stored in a storage region of a DRAM represented by a write address WADR. Thereafter, a timing at which a phase difference calculation circuit reads the focus detection signals stored in a storage region of the DRAM represented by a read address RADR in order to calculate a phase difference is illustrated.
FIG. 10A illustrates a timing of reading signals from pixels of the solid-state imaging device when a set of focus detecting pixels are arranged in the same row in the horizontal direction in the imaging region. FIG. 10B illustrates an example of a storage region of a DRAM in which the read focus detection signals are stored. FIG. 10C illustrates a timing of reading signals from pixels of the solid-state imaging device when a set of focus detecting pixels are arranged in the same column in the vertical direction in the imaging region, and FIG. 10D illustrates an example of a storage region of a DRAM in which the read focus detection signals are stored.
As can be seen from FIG. 10A, when a set of focus detecting pixels is arranged in the same row in the horizontal direction in the imaging region, a set of focus detection signals is consecutively included in the pixel signal read from the solid-state imaging device. Thus, the separating circuit can consecutively separate the focus detection signals from the read pixel signal and sequentially store the focus detection signals in consecutive storage regions in the DRAM. Due to this operation, the phase difference calculation circuit can sequentially read the focus detection signals stored in the consecutive storage regions in the DRAM consecutively and perform a calculation of a phase difference.
FIG. 10A illustrates pixel signals when 50 sets of focus detecting pixels, that is, 100 focus detecting pixels, are arranged at two positions in the same row. The separating circuit sequentially stores focus detection signals AF1 to AF100 and focus detection signals AF101 to AF200 read from respective focus detecting pixel groups in consecutive storage regions of the DRAM corresponding to write addresses WADR1 to WADR100 and write addresses WADR101 to WADR200. Accordingly, as can be seen from FIG. 10B, the focus detection signals AF1 to AF100 and the focus detection signals AF101 to AF200 are stored in the consecutive storage regions of the DRAM. Thereafter, the phase difference calculation circuit sequentially reads the focus detection signals AF1 to AF100 and the focus detection signals AF101 to AF200 stored in consecutive storage regions of the DRAM corresponding to read addresses RADR1 to RADR100 and read addresses RADR101 to RADR200, and performs a calculation of a phase difference.
As described above, when a set of focus detecting pixels are arranged in the same row in the horizontal direction in the imaging region, the separating circuit can consecutively store the focus detection signals separated from the pixel signals in the DRAM, and the phase difference calculation circuit can consecutively read the stored focus detection signals from the DRAM. Since such consecutive access to the DRAM can be performed through burst access of a DRAM, it is an efficient access technique from a point of view of a bus band of a DRAM in the imaging device.
However, as can be seen from FIG. 10C, when a set of focus detecting pixels are arranged in the same column in the vertical direction in the imaging region, that is, when a set of focus detecting pixels is arranged in different rows in the horizontal direction in the imaging region, a set of focus detection signals are separately included in the pixel signals read from the solid-state imaging device at timings synchronized with the different horizontal synchronous signals HD. For this reason, the separating circuit individually separates the focus detection signals from the pixel signals read at timings of the different horizontal synchronous signals HD, and stores the respective focus detection signals in separate storage regions of the DRAM. Due to this operation, the phase difference calculation circuit reads the respective focus detection signals stored in the separate storage regions of the DRAM, and performs a calculation of a phase difference.
FIG. 10C illustrates pixel signals when 50 sets of focus detecting pixels, that is, 100 focus detecting pixels, are arranged such that focus detecting pixels arranged in the same column are arranged at three positions (three columns) in the horizontal direction. The separating circuit sequentially stores the focus detection signals read from the respective focus detecting pixel groups for each of rows of the pixel signals in the consecutive storage regions of the DRAM corresponding to the write addresses WADR. More specifically, the separating circuit separates the focus detection signal AF1, the focus detection signal AF101, and the focus detection signal AF201 from the pixel signal of the first row, and sequentially stores the focus detection signal AF1, the focus detection signal AF101, and the focus detection signal AF201 in consecutive storage regions of the DRAM corresponding to write addresses WADR1 to WADR3. Further, the separating circuit separates the focus detection signal AF2, the focus detection signal AF102, and the focus detection signal AF202 from the pixel signal of the second row, and sequentially stores the focus detection signal AF2, the focus detection signal AF102, and the focus detection signal AF202 in consecutive storage regions of the DRAM corresponding to write addresses WADR4 to WADR6. Further, the separating circuit separates the focus detection signal AF3, the focus detection signal AF103, and the focus detection signal AF203 from the pixel signal of the third row, and sequentially stores the focus detection signal AF3, the focus detection signal AF103, and the focus detection signal AF203 in consecutive storage regions of the DRAM corresponding to write addresses WADR7 to WADR9.
Thus, as can be seen from FIG. 10D, a set of focus detection signals (for example, the focus detection signal AF1 and the focus detection signal AF2) is separately stored such that the focus detection signal AF1, the focus detection signal AF101, the focus detection signal AF201, the focus detection signal AF2, the focus detection signal AF102, the focus detection signal AF202, and the like are stored in the consecutive storage regions of the DRAM.
Thereafter, the phase difference calculation circuit reads a set of focus detection signals stored in the separate storage regions of the DRAM, and performs a calculation of a phase difference. More specifically, the phase difference calculation circuit reads the focus detection signal AF1, the focus detection signal AF2, and the focus detection signal AF3 stored in the storage regions corresponding to the read address RADR1, the read address RADR4, and the read address RADR7 to which the focus detecting pixels arranged in the first column are output, and performs a calculation of a phase difference. Further, the phase difference calculation circuit reads the focus detection signal AF101, the focus detection signal AF102, and the focus detection signal AF103 stored in the storage regions corresponding to the read address RADR2, the read address RADR5, and the read address RADR8 to which the focus detecting pixels arranged in the second column are output, and performs a calculation of a phase difference. Further, the phase difference calculation circuit reads the focus detection signal AF201, the focus detection signal AF202, and the focus detection signal AF203 stored in the storage regions corresponding to the read address RADR3, the read address RADR6, and the read address RADR9 to which the focus detecting pixels arranged in the third column are output, and performs a calculation of a phase difference.